Performing Normal Receive And Transmit Operation - Altera cyclone V Technical Reference

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Performing Normal Receive and Transmit Operation

of the PHY before reading or writing. Bit 0 indicates if the PHY is busy and is set before reading or
writing to the PHY management interface. †
2. Read the 16-bit data of the
mode of operation, by specifying the appropriate address value in bits[15:11] of the
Register
3. Provide the MAC address registers (
Register
4. Program the
5. Program the following fields to set the appropriate filters for the incoming frames in the
Filter Register
• Receive All †
• Promiscuous mode †
• Hash or Perfect Filter †
• Unicast, multicast, broadcast, and control frames filter settings †
6. Program the following fields for proper flow control in the
• Pause time and other pause frame control bits †
• Receive and Transmit Flow control bits †
• Flow Control Busy/Backpressure Activate †
7. Program the
8. Program the appropriate fields in
operation modes. After basic configuration is written, set bit 3 (
enable the receive and transmit state machines. †
Note: Do not change the configuration (such as duplex mode, speed, port, or loopback) when the
EMAC DMA is actively transmitting or receiving. Software should change these parameters only
when the EMAC DMA transmitter and receiver are not active.
Performing Normal Receive and Transmit Operation
For normal operation, perform the following steps: †
1. For normal transmit and receive interrupts, read the interrupt status. Then, poll the descriptors,
reading the status of the descriptor owned by the Host (either transmit or receive). †
2. Set appropriate values for the descriptors, ensuring that transmit and receive descriptors are owned by
the DMA to resume the transmission and reception of data. †
3. If the descriptors are not owned by the DMA (or no descriptor is available), the DMA goes into
SUSPEND state. The transmission or reception can be resumed by freeing the descriptors and issuing a
poll demand by writing 0 into the TX/RX poll demand registers, (Register 1 (Transmit Poll Demand
Register) and Register 2 (Receive Poll Demand Register)). †
4. The values of the current host transmitter or receiver descriptor address pointer can be read for the
debug process (Register 18 (Current Host Transmit Descriptor Register) and Register 19 (Current Host
Receive Descriptor Register)). †
5. The values of the current host transmit buffer address pointer and receive buffer address pointer can be
read for the debug process (Register 20 (Current Host Transmit Buffer Address Register) and Register
21 (Current Host Receive Buffer Address Register)). †
Stopping and Starting Transmission
Perform the following steps to pause the transmission for some time: †
Altera Corporation
GMII Data Register
. †
and
MAC Address0 Low Register
Hash Table Registers
: †
Interrupt Mask Register
MAC Configuration Register
from the PHY for link up, speed of operation, and
MAC Address0 High Register
through
MAC Address15 Low Register
0 through 7 (offset 0x500 to 0x51C).
Flow Control Register
bits, as required and if applicable for your configuration. †
GMII Address
through
MAC Address15 High
).
: †
to configure receive and transmit
) and bit 2 ( ) in this register to
TE RE
Ethernet Media Access Controller
cv_5v4
2016.10.28
MAC Frame
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