Altera cyclone V Technical Reference page 875

13-54
twhr2_and_we_2_re
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
global_int_enable Fields
Bit
8
error_rpt_disable
4
timeout_disable
0
flag
twhr2_and_we_2_re
Module Instance
nandregs
Offset:
0x100
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
Altera Corporation
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Reserved
Name
Command and ECC uncorrectable failures will not be
reported when this bit is set
Watchdog timer logic will be de-activated when this
bit is set.
Host will receive an interrupt only when this bit is set.
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
Bit Fields
25 24 23 22
Reserved
9 8 7 6
error Reserved
_rpt_
disab
le
RW
0x0
Description
Base Address
0xFFB80000
21 20 19 18
5 4 3 2
timeo Reserved
ut_
disab
le
RW
0x0
Access
Register Address
0xFFB80100
NAND Flash Controller
cv_5v4
2016.10.28
17 16
1 0
flag
RW 0x0
Reset
RW 0x0
RW 0x0
RW 0x0
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