Altera cyclone V Technical Reference page 953

cv_5v4
2016.10.28
• Slave interface
• Register block
• FIFO buffer
• Interrupt control
• Internal DMA controller
Slave Interface
The host processor accesses the SD/MMC controller registers and data FIFO buffers through the slave
interface.
Register Block
The register block is part of the BIU and provides read and write access to the CSRs.
All registers reside in the BIU clock domain,
start command bit (
CIU operation are copied to the CIU block. During this time, software must not write to the registers that
are transferred from the BIU to the CIU. The software must wait for the hardware to reset the
bit to 0 before writing to these registers again. The register unit has a hardware locking feature to prevent
illegal writes to registers.
Registers Locked Out Pending Command Acceptance
After a command start is issued by setting the
cannot be rewritten until the command is accepted by the CIU:
• Command (
• Command argument (
• Byte count (
• Block size (
• Clock divider (
• Clock enable (
• Clock source (
• Timeout (
• Card type (
The hardware resets the
registers is attempted during this locked time, the write is ignored and the hardware lock write error bit
( ) is set to 1 in the raw interrupt status register (
hle
not masked for a hardware lock error, an interrupt is sent to the host.
Once a command is accepted, you can send another command to the CIU—which has a one-deep
command queue—under the following conditions:
• If the previous command is not a data transfer command, the new command is sent to the
SD/MMC/CE-ATA card once the previous command completes.
• If the previous command is a data transfer command and if the wait previous data complete bit
(
wait_prvdata_complete
sent to the SD/MMC/CE-ATA card only when the data transfer completes.
• If the
wait_prvdata_complete
soon as the previous command is sent. Typically, use this feature to stop or abort a previous data
transfer or query the card status in the middle of a data transfer.
SD/MMC Controller
Send Feedback
) of the command register (
start_cmd
†
)
cmd
†
)
cmdarg
†
)
bytcnt
†
)
blksiz
†
)
clkdiv
†
)
clkena
†
)
clksrc
†
)
tmout
†
)
ctype
bit after the CIU accepts the command. If a host write to any of these
start_cmd
) of the
cmd
bit is 0, the new command is sent to the SD/MMC/CE-ATA card as
. When a command is sent to a card by setting the
l4_mp_clk
) to 1, all relevant registers needed for the
cmd
bit of the
start_cmd
†
). Additionally, if the interrupt is enabled and
rintsts
†
register is set to 1 for the new command, the new command is
Slave Interface
register, the following registers
cmd
†
†
†
†
Altera Corporation
14-7
start_cmd