Altera cyclone V Technical Reference page 201

cv_5v4
2016.10.28
Note: By default, the boot ROM code always configures the I/O pins used by boot after a cold reset.
When CPU1 is released from reset and the boot ROM code is located at the CPU1 reset exception address
(for a typical case), the boot ROM reset handler code reads the address stored in the CPU1 start address
register (
cpu1startaddr
There can be up to four preloader images stored in flash memory. The (
the index of the preloader's last image that is loaded in the on-chip RAM.
The boot ROM software state register (
the boot ROM.
The following warmram related registers are used to configure the warm reset from on-chip RAM feature
and must be written by software prior to the warm reset occurring.
Table 5-3: The warmram Registers
Register
enable
datastart
length
execution
crc
The number of wait states applied to the boot ROM's read operation is determined by the wait state bit
(
waitstate
boot ROM. If software has changed the clock frequency of the
state is necessary to access the boot ROM. Set the
access of the boot ROM. The enable safe mode warm reset update bit controls whether the wait state bit is
updated during a warm reset.
L3 Interconnect
The System Manager provides remap bits to the L3 interconnect. These bits can remap the Boot ROM and
the On-chip RAM.
System Manager
Send Feedback
) and passes control to software at that address.
Name
Enable
Data start
Length
Execution offset
Expected CRC
) of the register. After the boot process, software might require reading the code in the
ctrl
) is a 32-bit general-purpose register reserved for
bootromswstate
Controls whether the boot ROM attempts to boot from
the contents of the on-chip RAM on a warm reset.
Contains the byte offset of the warm boot CRC validation
region in the on-chip RAM. The offset must be word-
aligned to an integer multiple of four.
Contains the length in bytes of the region in the on-chip
RAM available for warm boot CRC validation.
Contains a 16-bit offset into the on-chip RAM that the
boot code jumps to if the CRC validation succeeds. The
boot ROM appends 0xFFFF to the upper 16-bits of this
32-bit register value when it is read.
Contains the expected CRC of the region in the on-chip
RAM.
l3_main_clk
bit to add an additional wait state to the read
waitstate
L3 Interconnect
) register contains
initswlastld
Purpose
after reset, an additional wait
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5-7