Altera cyclone V Technical Reference page 290

5-96
Pin Mux Control Group Register Descriptions
MIXED2IO2
This register is used to control the peripherals connected to emac1_tx_d2 Only reset by a cold reset
(ignores warm reset). NOTE: These registers should not be modified after IO configuration.There is no
support for dynamically changing the Pin Mux selections.
MIXED2IO3
This register is used to control the peripherals connected to emac1_tx_d3 Only reset by a cold reset
(ignores warm reset). NOTE: These registers should not be modified after IO configuration.There is no
support for dynamically changing the Pin Mux selections.
MIXED2IO4
This register is used to control the peripherals connected to emac1_rx_clk Only reset by a cold reset
(ignores warm reset). NOTE: These registers should not be modified after IO configuration.There is no
support for dynamically changing the Pin Mux selections.
MIXED2IO5
This register is used to control the peripherals connected to emac1_rx_ctl Only reset by a cold reset
(ignores warm reset). NOTE: These registers should not be modified after IO configuration.There is no
support for dynamically changing the Pin Mux selections.
MIXED2IO6
This register is used to control the peripherals connected to emac1_rx_d2 Only reset by a cold reset
(ignores warm reset). NOTE: These registers should not be modified after IO configuration.There is no
support for dynamically changing the Pin Mux selections.
MIXED2IO7
This register is used to control the peripherals connected to emac1_rx_d3 Only reset by a cold reset
(ignores warm reset). NOTE: These registers should not be modified after IO configuration.There is no
support for dynamically changing the Pin Mux selections.
GPLINMUX48
Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects the input signal for GPIO/
LoanIO 48. Only reset by a cold reset (ignores warm reset). NOTE: These registers should not be modified
after IO configuration.There is no support for dynamically changing the Pin Mux selections.
GPLINMUX49
Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects the input signal for GPIO/
LoanIO 49. Only reset by a cold reset (ignores warm reset). NOTE: These registers should not be modified
after IO configuration.There is no support for dynamically changing the Pin Mux selections.
GPLINMUX50
Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects the input signal for GPIO/
LoanIO 50. Only reset by a cold reset (ignores warm reset). NOTE: These registers should not be modified
after IO configuration.There is no support for dynamically changing the Pin Mux selections.
GPLINMUX51
Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects the input signal for GPIO/
LoanIO 51. Only reset by a cold reset (ignores warm reset). NOTE: These registers should not be modified
after IO configuration.There is no support for dynamically changing the Pin Mux selections.
GPLINMUX52
Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects the input signal for GPIO/
LoanIO 52. Only reset by a cold reset (ignores warm reset). NOTE: These registers should not be modified
after IO configuration.There is no support for dynamically changing the Pin Mux selections.
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cv_5v4
2016.10.28
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