Document Revision History - Altera cyclone V Technical Reference

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Document Revision History

Document Revision History
Table 7-6: Document Revision History
Date
October 2016
May 2016
November 2015
May 2015
December 2014
June 2014
February 2014
December 2013
November 2012
June 2012
January 2012
Altera Corporation
Version
2016.10.28 Maintenance release
2016.05.03 Maintenance release
2015.11.02 Maintenance release
2015.05.04
• Reference AXI ID encoding in MPU chapter
• Add information about the SDRAM address space
2014.12.15
• Minor correction to table in "Available Address Maps"
• Add detail to "L3 Address Space"
2014.06.30
• Corrected master interconnect security properties for:
• Added address map and register descriptions
2014.02.28 Maintenance release
2013.12.30 Maintenance release
1.2 Minor updates.
1.1 • Added interconnect connectivity matrix.
• Rearranged functional description sections.
• Simplified address remapping section.
• Added address map and register definitions section.
1.0 Initial release.
• Ethernet MAC
• ETR
Changes
System Interconnect
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cv_5v4
2016.10.28