Altera cyclone V Technical Reference page 839

13-18
ECC
MAP10 commands in INCR4 format are written to the
as MAP10 commands in multitransaction format (described in the "Multi-Transaction DMA Command").
Table 13-15: MAP10 Burst DMA (INCR4) Command Structure
The following table lists the MAP10 burst DMA command structure. The burst DMA command carries
the same information as the multi-transaction DMA command-data pairs, but in a very different format.
Data Beat 15
Beat 0 0x2
Beat 1 (36) Memory address high
Beat 2 Memory address low
(36)
Beat 3 0x0
Note: INT controls the value of the
the end of the DMA transfer. INT can take on one of the following values:
0—Do not interrupt host. The
1—Interrupt host. The
You can optionally send the 16-bit fields in the above table to the NAND flash controller as four separate
bursts of length 1 in sequential order. Altera recommends this method.
If you want the NAND flash controller DMA to perform cacheable accesses, you must configure the cache
bits by writing the
controller DMA must be idle before you use the system manager to modify its cache capabilities.
Related Information
• Multi-Transaction DMA Command
MAP10 Command Format
•
System Manager
•
ECC
The NAND flash controller incorporates ECC logic to calculate and correct bit errors. The flash controller
uses a Bose-Chaudhuri-Hocquenghem (BCH) algorithm for detection of multiple errors in a page.
The NAND flash controller supports 512- and 1024-byte ECC sectors. The flash controller inserts ECC
check bits for every 512 or 1024 bytes of data, depending on the selected sector size. After 512 or 1024
bytes, the flash controller writes the ECC check bit information to the device page.
ECC information is striped in between 512 or 1024 bytes of data across the page. The NAND flash
controller reads ECC information in the same pattern and performs a calculation to check for the presence
of errors.
The buffer address in host memory, which must be aligned to 32 bits.
(36)
INT specifies the host interrupt to be generated at the end of the complete DMA transfer. For more
(37)
information about INT, see the Note at the bottom of this table.
Altera Corporation
14 13 12 11
0x0: read. 0x1: write.
dma_cmd_comp
dma_cmd_comp
bit is set to 1.
dma_cmd_comp p
register in the
l3master
on page 13-11
on page 5-1
register at offset 0x10 in
Data
10 9 8 7
<PP>=number of pages
INT Burst length
(37)
bit of the
intr_status0
bit is set to 0.
group in the system manager. The NAND flash
nandgrp
on page 13-15
nanddata
6 5 4 3 2
register in the
status
NAND Flash Controller
Send Feedback
cv_5v4
2016.10.28
, the same
1 0
group at