Hps Block Diagram And System Integration; Hps Block Diagram - Altera cyclone V Technical Reference

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HPS Block Diagram and System Integration

HPS Block Diagram and System Integration

HPS Block Diagram

Figure 1-2: HPS Block Diagram
FPGA Portion
L4, 32-Bit Bus
DAP
ETR
SD/MMC
EMAC
(2)
USB
OTG
(2)
NAND
Flash
L4, 32-Bit Bus
CAN
(2)
Altera Corporation
FPGA to HPS
Control
Masters
Block
FPGA-to-HPS
FPGA
Bridge
Manager
32-Bit 64-Bit AXI
L3 Interconnect
(NIC-301)
32-Bit
32-Bit
L3 Main
Switch
32-Bit
L3 Master
Peripheral
32-Bit
Switch 32-Bit
32-Bit
32-Bit
32-Bit
32-Bit
32-Bit
L3 Slave Peripheral Switch
32-Bit
Watchdog
2
Timer I C UART GPIO
Timer
(4) (4) (2) (3)
(2)
HPS to FPGA Lightweight HPS to FPGA
Slaves Slaves
32-, 64-, 128-Bit AXI 32-, 64-, 128-Bit AXI 32-Bit AXI
HPS-to-FPGA Lightweight
Bridge HPS-to-FPGA Bridge
64-Bit AXI 32-Bit AXI
MPU Subsystem
64-Bit
ACP ID
Mapper
64-Bit
32-Bit
STM
32-Bit
Boot ROM
64-Bit
On-Chip RAM
32-Bit
64-Bit
DMA
Quad
32-Bit
SPI
Flash
SPI Clock Reset Scan System
(4) Manager Manager Manager Manager
1 - 6
Masters
ARM Cortex-A9
MPCore
CPU0 CPU1
SCU
ACP
L2
Cache
SDRAM Controller Subsystem
SDRAM Controller
Altera PHY
Single-Port
DDR
Interface
Memory
PHY
Controller
HPS I/O Pins
External Memory
Introduction to the Hard Processor System
cv_5v4
2016.10.28
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