Configuration By Host - Altera cyclone V Technical Reference

cv_5v4
2016.10.28
Bit
tworowaddr
Related Information

Configuration by Host

Configuration by Host
If the system manager sets
the process described in "Discovery and Initialization". In this case, the host processor must configure the
flash controller.
When performance is not a concern in the design, the timing registers can be left unprogrammed.
Related Information
Bootstrap Setting Bits
•
For recommended configuration-by-host settings to enable the basic read, write, and erase operations
for a single-plane, 512 bytes/page device.
Discovery and Initialization
•
Recommended Bootstrap Settings for 512-Byte Page Device
Table 13-3: Recommended Bootstrap Settings for an 8-bit, 512-Byte Page Device
devices_connected
device_width
number_of_planes
device_main_area_size
device_spare_area_size
pages_per_block
NAND Page Main and Spare Areas
Each NAND page has a main area and a spare area. The main area is intended for data storage. The spare
area is intended for ECC and maintenance data, such as wear leveling information. Each block consists of
a group of pages.
(31) All registers are in the
NAND Flash Controller
Send Feedback
• 1—flash device supports two-cycle addressing
• 0—flash device support three-cycle addressing
on page 13-5
bootstrap_inhibit_init
on page 13-4
on page 13-3
(31)
Register
group.
config
Example Value for 512-Byte Page
to 1, the NAND flash controller does not perform
1
0 indicating an 8-bit NAND flash device
1 indicating a single-plane device
The value of this register must reflect the flash device's
page main area size.
The value of this register must reflect the flash device's
page spare area size.
The value of this register must reflect number of pages per
block in the flash device.
Configuration by Host
Value
Altera Corporation
13-5