Altera cyclone V Technical Reference page 85

2-48
Peripheral PLL Group Register Descriptions
stat Fields
Bit
5:0
outresetack
Peripheral PLL Group Register Descriptions
Contains registers with settings for the Peripheral PLL.
Offset:
0x80
vco on page 2-49
Contains settings that control the Peripheral PLL VCO. The VCO output frequency is the input frequency
multiplied by the numerator (M+1) and divided by the denominator (N+1). Fields are only reset by a cold
reset.
misc
on page 2-51
Contains VCO control signals and other PLL control signals need to be controllable through register.
Fields are only reset by a cold reset.
emac0clk
Contains settings that control clock emac0_clk generated from the C0 output of the Peripheral PLL. Only
reset by a cold reset.
emac1clk
Contains settings that control clock emac1_clk generated from the C1 output of the Peripheral PLL. Only
reset by a cold reset.
perqspiclk
Contains settings that control clock periph_qspi_clk generated from the C2 output of the Peripheral PLL.
Only reset by a cold reset.
pernandsdmmcclk
Contains settings that control clock periph_nand_sdmmc_clk generated from the C3 output of the
Peripheral PLL. Only reset by a cold reset.
Altera Corporation
Name
These read only bits per PLL output indicate that the
PLL has received the Output Reset Counter request
and has gracefully stopped the respective PLL output
clock. For software to change the PLL output counter
without producing glitches on the respective clock,
SW must set the VCO register respective Output
Counter Reset bit. Software then polls the respective
Output Counter Reset Acknowledge bit in the Output
Counter Reset Ack Status Register. Software then
writes the appropriate counter register, and then
clears the respective VCO register Output Counter
Reset bit. The reset value of this bit is applied on a
cold reset; warm reset has no effect on this bit.
Value
0x0
0x1
on page 2-52
on page 2-53
on page 2-53
on page 2-54
Description
Description
Idle
Output Counter Acknowledge received.
cv_5v4
2016.10.28
Access Reset
RO 0x0
Clock Manager
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