Altera cyclone V Technical Reference page 268

5-74
l2
emac1
on page 5-80
This register is used to enable ECC on the EMAC1 RAM. ECC errors can be injected into the write path
using bits in this register. This register contains interrupt status of the ECC single/double bit error. Only
reset by a cold reset (ignores warm reset).
dma
on page 5-82
This register is used to enable ECC on the DMA RAM. ECC errors can be injected into the write path
using bits in this register. This register contains interrupt status of the ECC single/double bit error. Only
reset by a cold reset (ignores warm reset).
can0
on page 5-83
This register is used to enable ECC on the CAN0 RAM. ECC errors can be injected into the write path
using bits in this register. This register contains interrupt status of the ECC single/double bit error. Only
reset by a cold reset (ignores warm reset).
can1 on page 5-84
This register is used to enable ECC on the CAN1 RAM. ECC errors can be injected into the write path
using bits in this register. This register contains interrupt status of the ECC single/double bit error. Only
reset by a cold reset (ignores warm reset).
nand on page 5-85
This register is used to enable ECC on the NAND RAM. ECC errors can be injected into the write path
using bits in this register. This register contains interrupt status of the ECC single/double bit error. Only
reset by a cold reset (ignores warm reset).
qspi
on page 5-87
This register is used to enable ECC on the QSPI RAM. ECC errors can be injected into the write path
using bits in this register. This register contains interrupt status of the ECC single/double bit error. Only
reset by a cold reset (ignores warm reset).
sdmmc
on page 5-88
This register is used to enable ECC on the SDMMC RAM.ECC errors can be injected into the write path
using bits in this register. Only reset by a cold reset (ignores warm reset).
l2
This register is used to enable ECC on the L2 Data RAM. ECC errors can be injected into the write path
using bits in this register. This register is reset by a cold reset (ignores warm reset). The interrupt status of
the L2 ECC single/double bit error is handled in the General Interrupt Controller (GIC).
Module Instance
sysmgr
Offset:
0x140
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
Altera Corporation
0xFFD08000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
Base Address
2016.10.28
Register Address
0xFFD08140
System Manager
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cv_5v4