Altera cyclone V Technical Reference page 87

2-50
vco
vco Fields
Bit
31
regextsel
30:25
outreset
24
outresetall
23:22
psrc
Altera Corporation
Name
If set to '1', the external regulator is selected for the
PLL. If set to '0', the internal regulator is slected. It is
strongly recommended to select the external regulator
while the PLL is not enabled (in reset), and then
disable the external regulater once the PLL becomes
enabled. Software should simulateously update the
'Enable' bit and the 'External Regulator Input Select'
in the same write access to the VCO register. When
the 'Enable' bit is clear, the 'External Regulator Input
Select' should be set, and vice versa. The reset value of
this bit is applied on a cold reset; warm reset has no
effect on this bit.
Resets the individual PLL output counter. For
software to change the PLL output counter without
producing glitches on the respective clock, SW must
set the VCO register respective Output Counter Reset
bit. Software then polls the respective Output Counter
Reset Acknowledge bit in the Output Counter Reset
Ack Status Register. Software then writes the
appropriate counter register, and then clears the
respective VCO register Output Counter Reset bit.
LSB 'outreset[0]' corresponds to PLL output clock C0,
etc. If set to '1', reset output divider, no clock output
from counter. If set to '0', counter is not reset. The
reset value of this bit is applied on a cold reset; warm
reset has no effect on this bit.
Before releasing Bypass, All Output Counter Reset
must be set and cleared by software for correct clock
operation. If '1', Reset phase multiplexer and all
output counter state. So that after the assertion all the
clocks output are start from rising edge align. If '0',
phase multiplexer and output counter state not reset
and no change to the phase of the clock outputs.
Controls the VCO input clock source. Qsys and user
documenation refer to f2s_periph_ref_clk as f2h_
periph_ref_clk.
Value
0x0
0x1
0x2
Description
Description
eosc1_clk
eosc2_clk
f2s_periph_ref_clk
cv_5v4
2016.10.28
Access Reset
RW 0x1
RW 0x0
RW 0x0
RW 0x0
Clock Manager
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