Altera cyclone V Technical Reference page 329

cv_5v4
2016.10.28
GENERALIO10 Fields
Bit
1:0
sel
GENERALIO11
This register is used to control the peripherals connected to spim0_miso Only reset by a cold reset (ignores
warm reset). NOTE: These registers should not be modified after IO configuration.There is no support for
dynamically changing the Pin Mux selections.
Module Instance
sysmgr
Offset:
0x4AC
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
GENERALIO11 Fields
Bit
1:0
sel
System Manager
Send Feedback
Name
Select peripheral signals connected spim0_mosi. 0 :
Pin is connected to GPIO/LoanIO number 58. 1 : Pin
is connected to Peripheral signal UART0.RTS. 2 : Pin
is connected to Peripheral signal I2C1.SCL. 3 : Pin is
connected to Peripheral signal SPIM0.MOSI.
0xFFD08000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Name
Select peripheral signals connected spim0_miso. 0 :
Pin is connected to GPIO/LoanIO number 59. 1 : Pin
is connected to Peripheral signal UART1.CTS. 2 : Pin
is connected to Peripheral signal CAN1.RX. 3 : Pin is
connected to Peripheral signal SPIM0.MISO.
Description
Base Address
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Reserved
Description
GENERALIO11
Access
Register Address
0xFFD084AC
21 20 19 18
5 4 3 2
Access
5-135
Reset
RW 0x0
17 16
1 0
sel
RW 0x0
Reset
RW 0x0
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