Altera cyclone V Technical Reference page 511

Hard processor system
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cv_5v4
2016.10.28
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31
30
15
14
periph_id_2 Fields
Bit
7:0
rev_jepcode_jep6to4
periph_id_3
Peripheral ID3
Module Instance
l3regs
Offset:
0x1FEC
Access:
RO
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31
30
15
14
System Interconnect
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software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29
28
27
26
13
12
11
10
Reserved
Name
Revision, JEP106 code flag, JEP106[6:4]
0xFF800000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29
28
27
26
13
12
11
10
Reserved
Bit Fields
25
24
23
22
Reserved
9
8
7
6
Description
Base Address
Bit Fields
25
24
23
22
Reserved
9
8
7
6
rev_and
RO 0x0
periph_id_3
21
20
19
18
5
4
3
2
rev_jepcode_jep6to4
RO 0x6B
Access
Register Address
0xFF801FEC
21
20
19
18
5
4
3
2
cust_mod_num
RO 0x0
7-63
17
16
1
0
Reset
RO
0x6B
17
16
1
0
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