Document Revision History - Altera cyclone V Technical Reference

cv_5v4
2016.10.28
Module Instance
sdr
Offset:
0x50BC
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
mpweight_3_4 Fields
Bit
17:0
sumofweights_63_46

Document Revision History

Date
October 2016
May 2016
SDRAM Controller Subsystem
Send Feedback
0xFFC20000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Name
Set the sum of static weights for particular user
priority. This register is used as part of the deficit
round robin implementation. It should be set to the
sum of the weights for the ports
Version
2016.10.28 Maintenance release
2016.05.03 Maintenance release
Base Address
Bit Fields
25 24 23 22
Reserved
9 8 7 6
sumofweights_63_46
RW 0x0
Description
Document Revision History
Register Address
0xFFC250BC
21 20 19 18
5 4 3 2
Access
Changes
11-77
17 16
sumofweights_
63_46
RW 0x0
1 0
Reset
RW 0x0
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