Features Of The Cortex-A9 Mpu Subsystem - Altera cyclone V Technical Reference

2016.10.28
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The hard processor system (HPS) in the Altera SoC device includes a stand-alone, full-featured ARM
Cortex-A9 MPCore, single- or dual-core 32-bit application processor. The Cortex-A9 microprocessor unit
(MPU) subsystem is composed of a Cortex-A9 MPCore, a level 2 (L2) cache, an Accelerator Coherency
Port (ACP) ID mapper, and debugging modules.

Features of the Cortex-A9 MPU Subsystem

The Altera Cortex-A9 MPU subsystem provides the following features:
• One or two ARM Cortex-A9 processors each with the following support modules:
• ARM NEON single instruction, multiple data (SIMD) coprocesoor
• Memory Management Unit (MMU)
• 32 KB instruction cache
• 32 KB data cache
• Private interval timer
• Private watchdog timer
• Interrupt controller
• Global timer
• Snoop control unit (SCU)
• Accelerator Coherency Port (ACP)
• ARM L2 cache controller
• TrustZone system security extensions
• Symmetric multiprocessing (SMP) and asymmetric multiprocessing (AMP) modes
• Debugging modules
The Cortex-A9 MPU incorporates the following core and L2 cache versions:
Table 9-1: Cortex-A9 MPU Module Versions
Cortex-A9 Core
L2-310 Level 2 Cache Controller
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Cortex-A9 Microprocessor Unit Subsystem
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