Altera cyclone V Technical Reference page 876

cv_5v4
2016.10.28
31 30
15 14
Reserved
twhr2_and_we_2_re Fields
Bit
13:8
twhr2
5:0
we_2_re
tcwaw_and_addr_2_data
Module Instance
nandregs
Offset:
0x110
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
Reserved
NAND Flash Controller
Send Feedback
29 28 27 26
13 12 11 10
twhr2
RW 0x14
Name
Signifies the number of controller clocks that should
be introduced between the last command of a random
data output command to the start of the data transfer.
Signifies the number of bus interface nand_mp_clk
clocks that should be introduced between write
enable going high to read enable going low. The
number of clocks is the function of device parameter
Twhr and controller clock frequency.
0xFFB80000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
tcwaw
RW 0x14
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Reserved
Description
Base Address
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Reserved
tcwaw_and_addr_2_data
21 20 19 18
5 4 3 2
we_2_re
RW 0x32
Access
Register Address
0xFFB80110
21 20 19 18
5 4 3 2
addr_2_data
RW 0x32
13-55
17 16
1 0
Reset
RW 0x14
RW 0x32
17 16
1 0
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