Altera cyclone V Technical Reference page 672

9-36
Control of the AXI User Sideband Signals
Interconnect
Master
DAP
SD/MMC
FPGA-to-
HPS bridge
Related Information
ACP ID Mapper Address Map and Register Definitions
This section lists the ACP ID Mapper register address map and describes the registers.
Control of the AXI User Sideband Signals
The ACP ID mapper module allows control of the AXI user sideband signal values. Not all masters drive
these signals, so the ACP ID mapper makes it possible to drive the 5-bit user sideband signal with either a
default value (in dynamic mode) or specific values (in fixed mode). The sideband signals are controlled
through the ACP port. Sideband signals
determines whether the transaction is a shared cache access.
There are registers available to configure the default values of the user sideband signals for all transactions,
and fixed values of these signals for particular transactions in fixed mapping mode. In dynamic mode, the
user sideband signals of incoming transactions are mapped with the default values stored in the register. In
fixed mapping mode, the input ID of the transaction is mapped to the 3-bit output ID and the user
sideband signals of the transaction are mapped with the values stored in the register that corresponds to
the output ID. One important exception, however, is that the ACP ID mapper always allows user sideband
signals from the FPGA-to-HPS bridge to pass through to the ACP regardless of the user sideband value
associated with the ID.
Note: For coherent, cacheable reads or writes, the
set to a binary value of 5'b11111 (coherent write back, write allocate inner cache attribute). This
configuration ensures that the inner cache policy matches the policy used for cacheable data written
by the processor.
Memory Region Remap
The ACP ID mapper has 1 GB of address space, which is by default a view into the bottom 1 GB of
SDRAM. The mapper also allows transactions to be routed to different 1 GB-sized memory regions, called
pages, in both dynamic and fixed modes. The two most significant bits of incoming 32-bit AXI address
signals are replaced with the 2-bit user-configured address page decode information. The page decoder
uses the values shown in
(23) Values are in binary. The letter
Altera Corporation
(23)
ID
0000 0000 0100 0000 0000 0100
1000 0000 0101 1000 0000 0101
The "
defined.
0xxx xxxx x000
Table 9-9.
denotes variable ID bits that each master passes with each transaction.
x
vid*rd.mid
"s in this field are user-
x
on page 9-37
convey the inner cache attributes and
AWUSER[4:1]
field of the
user
vid*wr.mid
0000 0000 0100
1000 0000 0101
The " "s in this field are user-
x
defined.
and registers must be
vid*rd vid*wr
Cortex-A9 Microprocessor Unit Subsystem
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2016.10.28
AWUSER[0]