Altera cyclone V Technical Reference page 177

4-34
gpio_int_polarity
31 30
15 14
Reserved
gpio_int_polarity Fields
Bit
11
fpo
10
cdp
9
nsp
8
ncp
Altera Corporation
29 28 27 26
13 12 11 10
fpo cdp
RW RW
0x0 0x0
Name
Controls the polarity of edge or level sensitivity for
FPGA_POWER_ON
0x0
0x1
Controls the polarity of edge or level sensitivity for
CONF_DONE Pin
0x0
0x1
Controls the polarity of edge or level sensitivity for
nSTATUS Pin
0x0
0x1
Controls the polarity of edge or level sensitivity for
nCONFIG Pin
0x0
0x1
Bit Fields
25 24 23 22
Reserved
9 8 7 6
nsp ncp prd pre
RW RW RW RW
0x0 0x0 0x0 0x0
Description
Value Description
Active low
Active high
Value Description
Active low
Active high
Value Description
Active low
Active high
Value Description
Active low
Active high
21 20 19 18
5 4 3 2
prr ccd crc id
RW RW RW RW
0x0 0x0 0x0 0x0
Access
cv_5v4
2016.10.28
17 16
1 0
cd ns
RW RW 0x0
0x0
Reset
RW 0x0
RW 0x0
RW 0x0
RW 0x0
FPGA Manager
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