Altera cyclone V Technical Reference page 883

13-62
multiplane_addr_restrict
two_row_addr_cycles Fields
Bit
0
flag
multiplane_addr_restrict
Address restriction for multiplane commands
Module Instance
nandregs
Offset:
0x1A0
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
multiplane_addr_restrict Fields
Bit
0
flag
ecc_correction
Correction capability required
Altera Corporation
Name
This flag must be set for devices which allow for 2
ROW address cycles instead of the usual 3. Alterna‐
tively, the TWOROWADDR field of the System
Manager NANDGRP_BOOTSTRAP register when
asserted will set this flag.
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Name
This flag must be set for devices which require that
during multiplane operations all but the address for
the last plane should have their address cycles tied
low. The last plane address cycles has proper values.
This ensures multiplane address restrictions in the
device.
Description
Base Address
0xFFB80000
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Reserved
Description
Access
Register Address
0xFFB801A0
21 20 19 18
5 4 3 2
Access
NAND Flash Controller
cv_5v4
2016.10.28
Reset
RW 0x0
17 16
1 0
flag
RW 0x0
Reset
RW 0x0
Send Feedback