Altera cyclone V Technical Reference page 58

Hard processor system
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cv_5v4
2016.10.28
Module Name
EMAC 1
USB 0
USB 1
NAND flash controller
OSC1 timer 0
OSC1 timer 1
SP timer 0
SP timer 1
2
I
C controller 0
2
I
C controller 1
2
I
C controller 2
2
I
C controller 3
UART controller 0
UART controller 1
Clock Manager
Send Feedback
System Clock Name
l4_mp_clk
emac1_clk
osc1_clk
usb_mp_clk
usb_mp_clk
nand_x_clk
nand_clk
osc1_clk
osc1_clk
l4_sp_clk
l4_sp_clk
l4_sp_clk
l4_sp_clk
l4_sp_clk
l4_sp_clk
l4_sp_clk
l4_sp_clk
Clock Usage By Module
Use
Master
EMAC 1 internal logic
IEEE 1588 timestamp
Master and Slave
Master and Slave
NAND high-speed master and
slave
NAND flash
OSC1 timer 0
OSC1 timer 1
SP timer 0
SP timer 1
2
I
C 0
2
I
C 1
2
I
C 2
2
I
C 3
UART 0
UART 1
Altera Corporation
2-21

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