Document Revision History - Altera cyclone V Technical Reference

cv_5v4
2016.10.28
stat Fields
Bit
5:0
outresetack

Document Revision History

Table 2-13: Document Revision History
Date
October 2016
May 2016
November 2015
May 2015
December 2014
June 2014
February 2014
December 2013
Clock Manager
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Name
These read only bits per PLL output indicate that the
PLL has received the Output Reset Counter request
and has gracefully stopped the respective PLL output
clock. For software to change the PLL output counter
without producing glitches on the respective clock,
SW must set the VCO register respective Output
Counter Reset bit. Software then polls the respective
Output Counter Reset Acknowledge bit in the Output
Counter Reset Ack Status Register. Software then
writes the appropriate counter register, and then
clears the respective VCO register Output Counter
Reset bit. The reset value of this bit is applied on a
cold reset; warm reset has no effect on this bit.
Value
0x0
0x1
Version
2016.10.28 Maintenance release.
2016.05.03 Maintenance release.
2015.11.02 Minor formatting updates.
2015.05.04 Minor formatting updates.
2014.12.15
FREF, FVCO, and FOUT Equations section updated. More informa‐
tion added about vco register, M and N equations.
Reference Clock information added to Clock Groups section.
2014.06.30
E0SC1 changed to HPS_CLK1
E0SC2 changed to HPS_CLK2
Added Address Map and Register Descriptions
2014.02.28
Updated content in the "Peripheral Clock Group" section
2013.12.30
Minor formatting updates.
Description
Description
Idle
Output Counter Acknowledge received.
Document Revision History
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Changes
2-73
Reset
RO 0x0
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