Altera cyclone V Technical Reference page 666

9-30
Configuring AxUSER[4:0] Sideband Signals
• The correct
accesses,
• If an HPS peripheral uses the ACP for coherent master accesses, then the
configured in the corresponding System Manager register for that peripheral and the ACP ID mapper
must be configured for the appropriate
• For FPGA masters,
Related Information
• System Manager
For more information about programming AxCACHE[3:0] through the System Manager
• ARM Architecture Reference Manual ARMv7-A and ARMv7-R Edition
For more information about the memory types and attributes and the memory order model.
Cortex-A9 MPCore Technical Reference Manual
•
For more information about the Accelerator Coherency Port
Configuring AxUSER[4:0] Sideband Signals
The following list highlights how to correctly derive and apply the correct
accesses.
•
AxUSER[0]
• Because the ACP has no inner cache policy,
attributes pass to the L2 cache controller and are used when the cache is operating in exclusive mode.
• For HPS masters,
• For FPGA masters,
Related Information
Cortex-A9 MPCore Technical Reference Manual
For more information about the Accelerator Coherency Port
Burst Sizes and Byte Strobes
The ACP improves system performance for hardware accelerators in the FPGA fabric. However, in order
to achieve high levels of performance, you must use the one of the optimized burst types. Other burst
configurations have significantly lower performance.
Recommended Burst Types
Table 9-6: Recommended Burst Types for Optimized Bursts
Burst Type
Wrapping
Incrementing
Note: If the slave port of the FPGA-to-HPS bridge is not 64 bits wide, you must supply bursts to the
FPGA-to-HPS bridge that are upsized or downsized to the burst types above. For example, if the
slave data width of the FPGA-to-HPS bridge is 32 bits, then bursts of eight beats by 32 bits are
required to access the ACP efficiently.
Altera Corporation
setting is dependent on the MMU page table settings. However, for coherent
AxCACHE[3:0]
must be set to 0x1.
AxCACHE[1]
AxCACHE[3:0]
on page 5-1
(shared attribute) must be set to 0x1 for coherent accesses.
is applied on the ACP ID Mapper.
AxUSER[4:0]
AxUSER[4:0]
Beats
4
4
properties.
AxUSER
is applied in the FPGA fabric and can be set for each access.
AxUSER[3:1]
is applied in the FPGA fabric and can be set for each access.
Width (Bits)
64
64
AxCACHE
settings for coherent
AxUSER
is not interpreted by the SCU.
Address Type
64-bit aligned Asserted
32-bit aligned Asserted
Cortex-A9 Microprocessor Unit Subsystem
cv_5v4
2016.10.28
properties must be
AxUSER[3:1]
Byte Strobes
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