Register Slave Interface - Altera cyclone V Technical Reference

15-8

Register Slave Interface

Register Slave Interface
The quad SPI flash controller uses the register slave interface to configure the quad SPI controller through
the quad SPI configuration registers, and to access flash memory under software control, through the
flashcmd
STIG Operation
The Software Triggered Instruction Generator (STIG) is used to access the volatile and non-volatile
configuration registers, the legacy SPI status register, and other status and protection registers. The STIG
also is used to perform ERASE functions. The direct and indirect access controllers are used only to
transfer data. The
the flash device:
• Instruction opcode
• Number of address bytes
• Number of dummy bytes
• Number of write data bytes
• Write data
• Number of read data bytes
The address is specified through the flash command address register (
have been specified, software can trigger the command with the execute command field (
flashcmd
of the
flashcmd
lower (
flashcmdrddatalo
to the flash command write data lower (
(
flashcmdwrdataup
Commands issued through the STIG have a higher priority than all other read accesses and therefore
interrupt any read commands being requested by the direct or indirect controllers. However, the STIG
does not interrupt a write sequence that may have been issued through the direct or indirect access
controller. In these cases, it might take a long time for the
indicates the operation is complete.
Note: Altera recommends using the STIG instead of the SPI legacy mode to access the flash device
registers and perform erase operations.
Local Memory Buffer
The SRAM local memory buffer is a 128 by 32-bit (512 total bytes) memory and includes support for error
correction code (ECC). The ECC logic provides outputs to notify the system manager when single-bit
correctable errors are detected (and corrected) and when double-bit uncorrectable errors are detected. The
ECC logic also allows the injection of single- and double-bit errors for test purposes.
Initialization of memory data before enabling ECC prevents spurious ECC interrupts when you enable
ECC for the first time.
The SRAM has two partitions, with the lower partition reserved for indirect read operations and the upper
partition reserved for indirect write operations, as shown in
specified in the SRAM partition register (
allocated to indirect read is (
–
srampart
indirect read partition size field (
(52) You cannot allocate all of the SRAM for writes.
Altera Corporation
register in the STIG.
register uses the following parameters to define the command to be issued to
flashcmd
register and wait for its completion by polling the command execution status bit (
register. A maximum of eight data bytes may be read from the flash command read data
) and flash command read data upper (
) registers per command.
srampart
) . For example, to specify four bytes of storage, write the value 1. The value written to the
(52)
addr
) and flash command write data upper
flashcmdwrdatalo
cmdexecstat
Figure
), based on 32-bit word sizes. The number of locations
srampart
+1); and the number of locations allocated to indirect write is (128
) defines the number of entries reserved for indirect read operations.
). Once these settings
flashcmdaddr
execcmd
) registers or written
flashcmdrddataup
bit of the
flashcmd
15-1. The size of each partition is
Quad SPI Flash Controller
cv_5v4
2016.10.28
) of the
)
cmdexecstat
register
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