Altera cyclone V Technical Reference page 269

cv_5v4
2016.10.28
31 30
15 14
l2 Fields
Bit
2
injd
1
injs
0
en
ocram
This register is used to enable ECC on the On-chip RAM. ECC errors can be injected into the write path
using bits in this register. This register contains interrupt status of the ECC single/double bit error. Only
reset by a cold reset (ignores warm reset).
Module Instance
sysmgr
Offset:
0x144
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
System Manager
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29 28 27 26
13 12 11 10
Reserved
Name
Changing this bit from zero to one injects a double,
non-correctable error into the L2 Data RAM. This
only injects one double bit error into the L2 Data
RAM.
Changing this bit from zero to one injects a single,
correctable error into the L2 Data RAM. This only
injects one error into the L2 Data RAM.
Enable ECC for L2 Data RAM
0xFFD08000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Description
Base Address
ocram
21 20 19 18
5 4 3 2
injd
RW
0x0
Access
Register Address
0xFFD08144
5-75
17 16
1 0
injs en
RW RW 0x0
0x0
Reset
RW 0x0
RW 0x0
RW 0x0
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