Fpga Manager Module Address Map - Altera cyclone V Technical Reference

4-10
data
data
Used to send configuration image to FPGA. The DATA register accepts 4 bytes of the configuration image
on each write. The configuration image byte-stream is converted into a 4-byte word with little-endian
ordering. If the configuration image is not an integer multiple of 4 bytes, software should pad the
configuration image with extra zero bytes to make it an integer multiple of 4 bytes. The FPGA Manager
converts the DATA to 16 bits wide when writing CB.DATA for partial reconfiguration. The FPGA
Manager waits to transmit the data to the CB until the FPGA is able to receive it. For a full configuration,
the FPGA Manager waits until the FPGA exits the Reset Phase and enters the Configuration Phase. For a
partial reconfiguration, the FPGA Manager waits until the CB.PR_READY signal indicates that the FPGA
is ready.
Module Instance
fpgamgrdata
Offset:
0x0
Access:
RW
31 30
15 14
data Fields
Bit
31:0
value

FPGA Manager Module Address Map

Registers in the FPGA Manager module accessible via its APB slave
Base Address:
Altera Corporation
29 28 27 26
13 12 11 10
Name
Accepts configuration image to be sent to CB when
the HPS configures the FPGA. Software normally just
writes this register. If software reads this register, it
returns the value 0 and replies with an AXI SLVERR
error.
0xFF706000
Base Address
0xFFB90000
Bit Fields
25 24 23 22
value
RW 0x0
9 8 7 6
value
RW 0x0
Description
Register Address
0xFFB90000
21 20 19 18
5 4 3 2
Access
cv_5v4
2016.10.28
17 16
1 0
Reset
RW 0x0
FPGA Manager
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