Altera cyclone V Technical Reference page 848

cv_5v4
2016.10.28
Locking All Memory Blocks
To lock the entire memory:
1. Write to the command register, setting the
address.
2. Write 0x21 to the
Setting Lock-Tight on All Memory Blocks
After the lock-tight is applied, unlocked areas cannot be locked, and locked areas cannot be unlocked. To
lock-tight the entire memory:
1. Write to the command register, setting the
address.
2. Write 0x31 to the
To disable the lock-tight, reset the memory controller.
Transfer Mode Operations
You can configure the NAND flash controller in one of the following modes of data transfer:
• Default area transfer mode
• Spare area transfer mode
• Main+spare area transfer mode
The NAND flash controller determines the default transfer mode from the setting of
transfer_spare_reg
transfer mode from the existing mode to the new mode. All subsequent commands are in the new mode of
transfer. You must consider that transfer modes can be changed at logical data transfer boundaries. For
example:
• At the beginning or end of a page in case of single page read or write.
• At the beginning or end of a complete multi-page pipeline read or write command.
transfer_spare_reg and MAP10 Transfer Mode Commands
The following table lists the functionality of the MAP10 transfer mode commands, and their mappings to
the
transfer_spare_reg
Table 13-17: transfer_spare_reg and MAP10 Transfer Mode Commands
transfer_spare_reg
0
0
0
1
Default access mode (0x42) maps to either main (only) or main+spare mode, depending on the value of
(39)
transfer_spare_reg
NAND Flash Controller
Send Feedback
register.
Data
register.
Data
register in the
config
register in the
config
MAP10 Transfer Mode Commands
.
field to 2 and the
CMD_MAP
field to 2 and the
CMD_MAP
group. Use MAP10 commands to dynamically change the
group.
0x42 Main
0x41 Spare
0x43 Main+spare
0x42 Main+spare
Locking All Memory Blocks
field to any memory
BLK_ADDR
field to any memory
BLK_ADDR
Resulting NAND Flash Controller
Mode
(39)
(39)
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