Card Read Threshold - Altera cyclone V Technical Reference

14-70

Card Read Threshold

The host controller uses the following settings while sending the RW_REG command for the STANDBY
IMMEDIATE ATA command:
• register setting:
cmd
•
cmdarg
• Bit [31] set to 1
• Bits [7:2] set to 4
• All other bits set to 0
• Task file settings:
• Command field of the ATA task file set to 0xEA
• Reserved fields of the task file set to 0
•
bytcnt
Card Read Threshold
When an application needs to perform a single or multiple block read command, the application must set
the
cardthrctl
(
cardrdthreshold
controller ensures that the controller sends a read command only if there is space equal to the card read
threshold available in the RX FIFO buffer. This in turn ensures that the card clock is not stopped in the
middle a block of data being transmitted from the card. Set the card read threshold to the block size of the
transfer to guarantee there is a minimum of one block size of space in the RX FIFO buffer before the
controller enables the card clock.
The card read threshold is required when the round trip delay is greater than half of
Table 14-36: Card Read Threshold Guidelines
Bus Speed
Modes
SDR25
SDR12
Related Information
Cyclone V Device Datasheet
(50) Delay_R = Delay_O + tODLY + Delay_I
†
Where:
Delay_O =
sdmmc_clk
Delay_I = Input I/O pin delay + routing delay to the input register
tODLY =
sdmmc_cclk_out
For the delay numbers needed for above calculation, refer to Cyclone V Datasheet.
Altera Corporation
†
data_expected
†
register settings:
†
†
†
†
register and
block_size
register with the appropriate card read threshold size in the card read threshold field
) and set the
cardrdthren
†
Round Trip Delay (Delay_R)
Delay_R > 0.5 * (
sdmmc_clk
Delay_R < 0.5 * (
sdmmc_clk
Delay_R > 0.5 * (
sdmmc_clk
Delay_R < 0.5 * (
sdmmc_clk
to
sdmmc_cclk_out
to card output delay (varies across card manufactures and speed modes)
†
bit set to 0
†
†
field of the register: set to 16
blksiz
bit to 1. This additional information specified in the
†
(50) Is Stopping of Card
Clock Allowed?
/4) No
/4) Yes
/4) No
/4) Yes
†
delay (including I/O pin delay)
†
sdmmc_clk_divided
Card Read Threshold Required?
Yes
No
Yes
No
†
†
†
cv_5v4
2016.10.28
†
.
†
SD/MMC Controller
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