Clock Manager Address Map And Register Definitions - Altera cyclone V Technical Reference

cv_5v4
2016.10.28
Module Name
L4 watchdog timer 1
SPI master controller 0
SPI master controller 1
SPI slave controller 0
SPI slave controller 1
Debug subsystem
Reset manager
Scan manager
Timestamp generator

Clock Manager Address Map and Register Definitions

The address map and register definitions for the HPS-FPGA bridge consist of the following regions:
• Clock Manager Module
Related Information
• Introduction to the Hard Processor System
The base addresses of all modules are also listed in the Introduction to the Hard Processor System
chapter.
http://www.altera.com/literature/hb/cyclone-v/hps.html
•
Clock Manager
Send Feedback
Clock Manager Address Map and Register Definitions
System Clock Name
osc1_clk
spi_m_clk
spi_m_clk
l4_main_clk
l4_main_clk
l4_mp_clk
dbg_clk
dbg_at_clk
dbg_trace_clk
osc1_clk
l4_sp_clk
spi_m_clk
dbg_timer_clk
on page 1-1
Use
L4 watchdog timer 1
SPI master 0
SPI master 1
SPI slave 0
SPI slave 1
System bus
Debug
Trace bus
Trace port
Reset manager
Slave
Scan manager
Timestamp generator
Altera Corporation
2-23