Hps Emac I/O Signals - Altera cyclone V Technical Reference

17-6

HPS EMAC I/O Signals

Figure 17-2: EMAC to FPGA Routing Example
SGMII
PHY
MDIO_0/I2C_2
RMII
PHY
MDIO_1/I2C_3
Note: The Micrel KSZ9021RN Ethernet PHY has been verified to work properly with the HPS EMAC and
is recommended for use in board design.
Related Information
EMAC FPGA Interface Initialization
Information on how to initialize GMII/MII interface
HPS EMAC I/O Signals
The following table lists the EMAC signals that are routed to the HPS pins. These signals provide the
RGMII interface.
Altera Corporation
XCVR
GMII to SGMII Adaptor
GMII to RMII Adaptor
GMII_0
MDIO_0/I2C_2
Pin
Multiplexer
TMSTP= Timestamp
TMSTP
PHY DMA
EMAC0
MDIO CSR
TMSTP
PHY DMA
EMAC1
MDIO CSR
I2C_2 (for Ethernet)
I2C_3 (for Ethernet)
on page 17-65
FPGA
1588
Control
AXI
APB
Interconnect
AXI
APB
HPS
Ethernet Media Access Controller
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cv_5v4
2016.10.28
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