Altera cyclone V Technical Reference page 958

14-12
FIFO Buffer
For example, on receiving the Receive FIFO Data Request interrupt, the FIFO buffer must be emptied so
that the FIFO buffer count is not greater than the RX watermark, which causes the interrupt to be
†
triggered.
The rest of the interrupts are triggered by single clock-pulse-width sources.
FIFO Buffer
The SD/MMC controller has a 4 KB data FIFO buffer for storing transmit and receive data. The FIFO
buffer memory supports error correction codes (ECCs). Both interfaces to the FIFO buffer support single
and double bit error injection. The enable and error injection pins are inputs driven by the system
manager and the status pins are outputs driven to the MPU subsystem.
The SD/MMC controller provides outputs to notify the system manager when single-bit correctable errors
are detected (and corrected), and when double-bit (uncorrectable) errors are detected. The system
manager generates an interrupt to the GIC when an ECC error is detected.
Note: Initialization of memory data before enabling ECC prevents spurious ECC interrupts when you
enable ECC for the first time.
Related Information
System Manager
Internal DMA Controller
Internal DMA controller (AHB Master) enables the core to act as a Master on the AHB to transfer data to
and from the AHB.
• Supports 32-bit data
• Supports split, retry, and error AHB responses, but does not support wrap
• Configurable for little-endian or big-endian mode
• Allows the selection of AHB burst type through software
The internal DMA controller has a CSR and a single transmit or receive engine, which transfers data from
system memory to the card and vice versa. The controller uses a descriptor mechanism to efficiently move
data from source to destination with minimal host processor intervention. You can configure the
controller to interrupt the host processor in situations such as transmit and receive data transfer
completion from the card, as well as other normal or error conditions. The DMA controller and the host
driver communicate through a single data structure.
The internal DMA controller transfers the data received from the card to the data buffer in the system
memory, and transfers transmit data from the data buffer in the memory to the controller's FIFO buffer.
Descriptors that reside in the system memory act as pointers to these buffers.
A data buffer resides in the physical memory space of the system memory and consists of complete or
partial data. The buffer status is maintained in the descriptor. Data chaining refers to data that spans
multiple data buffers. However, a single descriptor cannot span multiple data buffers.
A single descriptor is used for both reception and transmission. The base address of the list is written into
the descriptor list base address register (
can point back to the first entry to create a ring structure. The descriptor list resides in the physical
memory address space of the host. Each descriptor can point to a maximum of two data buffers.
Altera Corporation
on page 5-1
dbaddr
†
). A descriptor list is forward linked. The last descriptor
†
†
†
†
SD/MMC Controller
Send Feedback
cv_5v4
2016.10.28