Altera cyclone V Technical Reference page 786

11-48
dramtiming1
Bit
2:0
memtype
dramtiming1
This register implements JEDEC standardized timing parameters. It should be programmed in clock
cycles, for the value specified by the memory vendor.
Module Instance
sdr
Offset:
0x5004
Access:
RW
31 30
15 14
trrd
RW 0x0
dramtiming1 Fields
Bit
31:24
trfc
23:18
tfaw
17:14
trrd
Altera Corporation
Name
This bit field selects the memory type. This field can
be programmed with the following binary values:
Value
0x0
0x1
0x2
0x3
0x4
0x5-0x7
29 28 27 26
trfc
RW 0x0
13 12 11 10
tcl
RW 0x0
Name
The refresh cycle timing parameter.
The four-activate window timing parameter.
The activate to activate, different banks timing
parameter.
Description
Description
Reserved
Memory type is DDR2 SDRAM
Memory type is DDR3 SDRAM
reserved
Memory type is LPDDR2 SDRAM
Reserved
Base Address
0xFFC20000
Bit Fields
25 24 23 22
9 8 7 6
tal
RW 0x0
Description
Access
Register Address
0xFFC25004
21 20 19 18
tfaw
RW 0x0
5 4 3 2
Access
SDRAM Controller Subsystem
cv_5v4
2016.10.28
Reset
RW 0x0
17 16
trrd
RW 0x0
1 0
tcwl
RW 0x0
Reset
RW 0x0
RW 0x0
RW 0x0
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