Emac Signal Description - Altera cyclone V Technical Reference

cv_5v4
2016.10.28
Manager (
emac_ptp_clk
the
ptp_clk_sel

EMAC Signal Description

The EMAC provides a variety of PHY interfaces and control options through the HPS and the FPGA I/Os.
For designs in which the HPS is pin-limited, the EMAC signals can be routed through the FPGA as any
one of the following interfaces by using soft adaptor logic in the FPGA:
• RMII/RGMII
• MII/GMII
• SGMII
The figure below depicts a design which routes the EMAC0 and EMAC1 signals through the FPGA to
provide an RMII and SGMII interface.
Refer to the "EMAC FPGA Interface Initialization" section to find out more information about configuring
EMAC interfaces through FPGA.
Ethernet Media Access Controller
Send Feedback
) or the FPGA fabric (
bit in the register in the system manager.
emac_global
). The clock reference is selected by
f2s_emac_ptp_ref_clk
EMAC Signal Description
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