Altera cyclone V Technical Reference page 595

cv_5v4
2016.10.28
comp_id_0 Fields
Bit
7:0
preamble
comp_id_1
Component ID1
Module Instance
fpga2hpsregs
Offset:
0x1FF4
Access:
RO
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
comp_id_1 Fields
Bit
7:0
genipcompcls_preamble
comp_id_2
Component ID2
Module Instance
fpga2hpsregs
Offset:
0x1FF8
Access:
RO
HPS-FPGA Bridges
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Name
Preamble
0xFF600000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Reserved
Name
Generic IP component class, Preamble
0xFF600000
Description
Base Address
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Description
Base Address
comp_id_1
Access
Register Address
0xFF601FF4
21 20 19 18
5 4 3 2
genipcompcls_preamble
RO 0xF0
Access
Register Address
0xFF601FF8
8-13
Reset
RO 0xD
17 16
1 0
Reset
RO 0xF0
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