Altera cyclone V Technical Reference page 780

11-42
SDRAM Controller Address Map
Register
dramaddrw on page 11-
53
dramifwidth
11-54
dramsts on page 11-
55
dramintr on page 11-
56
sbecount on page 11-
57
dbecount on page 11-
58
erraddr on page 11-
58
dropcount on page 11-
59
dropaddr on page 11-
60
lowpwreq on page 11-
60
lowpwrack on page 11-
61
staticcfg on page 11-
62
ctrlwidth on page 11-
63
portcfg on page 11-
64
fpgaportrst
11-66
protportdefault
page 11-67
protruleaddr
11-68
protruleid on page
11-69
protruledata
11-70
protrulerdwr
11-71
Altera Corporation
Offset
0x502C
on page 0x5030
0x5038
0x503C
0x5040
0x5044
0x5048
0x504C
0x5050
0x5054
0x5058
0x505C
0x5060
0x507C
on page 0x5080
on 0x508C
on page 0x5090
0x5094
on page 0x5098
on page 0x509C
Width Acces Reset Value
s
32 RW 0x0
32 RW 0x0
32 RW 0x0
32 RW 0x0
32 RW 0x0
32 RW 0x0
32 RW 0x0
32 RW 0x0
32 RW 0x0
32 RW 0x0
32 RW 0x0
32 RW 0x0
32 RW 0x0
32 RW 0x0
32 RW 0x0
32 RW 0x0
32 RW 0x0
32 RW 0x0
32 RW 0x0
32 RW 0x0
Description
DRAM Address Widths Register
DRAM Interface Data Width
Register
DRAM Status Register
ECC Interrupt Register
ECC Single Bit Error Count
Register
ECC Double Bit Error Count
Register
ECC Error Address Register
ECC Auto-correction Dropped
Count Register
ECC Auto-correction Dropped
Address Register
Low Power Control Register
Low Power Acknowledge Register
Static Configuration Register
Memory Controller Width
Register
Port Configuration Register
FPGA Ports Reset Control
Register
Memory Protection Port Default
Register
Memory Protection Address
Register
Memory Protection ID Register
Memory Protection Rule Data
Register
Memory Protection Rule Read-
Write Register
SDRAM Controller Subsystem
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cv_5v4
2016.10.28