Altera cyclone V Technical Reference page 49

2-12
Peripheral Clock Group
Table 2-7: Peripheral PLL Output Assignments
PLL
Peripheral
The following figure shows programmable post-PLL dividers and clock gating for the peripheral clock
group. Clock gate blocks in the diagram indicate clocks that may be gated off under software control.
Software is expected to gate these clocks off prior to changing any PLL or divider settings that might create
incorrect behavior on these clocks.
Altera Corporation
Output Counter
C0
C1
C2
C3
C4
C5
Clock Name
Up to 250 MHz
emac0_base_clk
Up to 250 MHz
emac1_base_clk
Up to 432 MHz
periph_qspi_
base_clk
Up to 250 MHz for
periph_nand_
the NAND flash
sdmmc_base_clk
controller and up to
200 MHz for the SD/
MMC controller
Up to 240 MHz for
periph_base_
the SPI masters and
base_clk
up to 200 MHz for
the scan manager
osc1_clk
h2f_user1_base_
100 MHz
clk
Frequency Phase Shift Control
No
No
No
No
No
to No
cv_5v4
2016.10.28
Clock Manager
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