Altera cyclone V Technical Reference page 734
Hard processor system
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Also See for cyclone V:
- Device handbook (1077 pages) ,
- User manual (136 pages) ,
- Reference manual (66 pages)
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10-24
Debug Access Port (DAP) Module Address Map
Register Group
ETR
CTI FPGA
FPGA ROM
FPGA CoreSight
Components
Cortex-A9 ROM
CPU0 Debug
CPU0 PMU
CPU1 Debug
CPU1 PMU
CTI0
CTI1
Altera Corporation
Description
This address space is
allocated for the
Embedded Trace
Router.
This address space is
allocated for the Cross-
Trigger Interface of the
FPGA.
This address space is
allocated for the FPGA
ROM.
This address space is
allocated for the FPGA
CoreSight
Components.
This address space is
allocated for the
Cortex-A9 ROM.
This address space is
allocated for CPU0
Debug.
This address space is
allocated for the CPU0
PMU.
This address space is
allocated for CPU1
Debug.
This address space is
allocated for the CPU1
PMU.
This address space is
allocated for Cross-
Trigger Interface 0
(CTI0).
This address space is
allocated for Cross-
Trigger Interface 1
(CTI1)
Start Address
0xFF006000
0xFF007000
0xFF080000
0xFF081000
0xFF100000
0xFF110000
0xFF111000
0xFF112000
0xFF113000
0xFF118000
0xFF119000
cv_5v4
2016.10.28
End Address
0xFF006FFF
0xFF007FFF
0xFF080FFF
0xFF0FF000
0xFF10FFFF
0xFF110FFF
0xFF111FFF
0xFF112FFF
0xFF117FFF
0xFF118FFF
0xFF11BFFF
CoreSight Debug and Trace
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