Initialization - Altera cyclone V Technical Reference

cv_5v4
2016.10.28
Table 11-12: Command Port Assignments
Command Port
0, 2, 4
1, 3, 5
6
7
8
9
Table 11-13: Read Port Assignments
Read Port
0, 1, 2, 3
4
5
Table 11-14: Write Port Assignments
Write Port
0, 1, 2, 3
4
5

Initialization

The SDRAM controller subsystem has control and status registers (CSRs) which control the operation of
the controller including DRAM type, DRAM timing parameters and relative port priorities. It also has a
small set of bits which depend on the FPGA fabric to configure ports between the memory controller and
SDRAM Controller Subsystem
Send Feedback
FPGA fabric AXI read command ports
FPGA fabric Avalon-MM read or write command ports
FPGA fabric AXI write command ports
FPGA fabric Avalon-MM read or write command ports
L3 AXI read command port
MPU AXI read command port
L3 AXI write command port
MPU AXI write command port
64-bit read data from the FPGA fabric. When 128-bit data read ports are
created, then read data ports 0 and1 get paired as well as 2 and 3.
32-bit L3 read data port
64-bit MPU read data port
64-bit write data from the FPGA fabric. When 128-bit data write ports are
created, then write data ports 0 and 1 get paired as well as 2 and 3.
32-bit L3 write data port
64-bit MPU write data port
Allowed Functions
Allowed Functions
Allowed Functions
11-27
Initialization
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