Altera cyclone V Technical Reference page 530

7-82
NANDREGS Register Descriptions
31 30
15 14
ahb_cntl Fields
Bit
1
force_incr
0
decerr_en
NANDREGS Register Descriptions
Registers associated with the NANDREGS master. This master is used to access the registers in the NAND
flash controller.
Offset:
0x1f000
fn_mod_bm_iss
Sets the issuing capability of the preceding switch arbitration scheme to multiple or single outstanding
transactions.
fn_mod on page 7-83
Sets the block issuing capability to multiple or single outstanding transactions.
fn_mod_bm_iss
Sets the issuing capability of the preceding switch arbitration scheme to multiple or single outstanding
transactions.
Altera Corporation
29 28 27 26
13 12 11 10
Name
Value
0x0
0x1
Value
0x0
0x1
on page 7-82
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Reserved
Description
Description
Multiple outstanding write transactions
If a beat is received that has no write data
strobes set, that write data beat is replaced
with an IDLE beat. Also, causes all transac‐
tions that are to be output to the AHB
domain to be an undefined length INCR.
Description
No DECERR response.
If the AHB protocol conversion function
receives an unaligned address or a write data
beat without all the byte strobes set, creates a
DECERR response.
21 20 19 18
5 4 3 2
Access
System Interconnect
cv_5v4
2016.10.28
17 16
1 0
force decerr_
_incr en
RW RW 0x0
0x0
Reset
RW 0x0
RW 0x0
Send Feedback