Coresight Debug And Trace - Altera cyclone V Technical Reference

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SPI Master Controllers
SPI Master Controllers
The two SPI master controllers are based on Synopsys DesignWare Synchronous Serial Interface (SSI)
controller and offer the following features:
• Choice of Motorola
ductor
®
• Programmable data frame size from 4 bits to 16 bits
• Supports full- and half-duplex modes
• Supports up to four chip selects
• Direct access for host processor
• DMA controller may be used for large transfers
• Programmable master serial bit rate
• Support for
• Transmit and receive FIFO buffers are 256 words deep
Related Information
SPI Controller
SPI Slave Controllers
The two SPI slave controllers are based on Synopsys DesignWare Synchronous Serial Interface (SSI)
controller and offer the following features:
• Programmable data frame size from 4 bits to 16 bits
• Supports full- and half-duplex moces
• Direct access for host processor
• DMA controller may be used for large transfers
• Transmit and receive FIFO buffers are 256 words deep
Related Information
SPI Controller
GPIO Interfaces
The HPS provides three GPIO interfaces that are based on Synopsys DesignWare APB General Purpose
Programming I/O peripheral and offer the following features:
• Supports digital de-bounce
• Configurable interrupt mode
• Supports up to 67 dedicated I/O pins and an additional 14 input-only pins
Related Information
General-Purpose I/O Interface

CoreSight Debug and Trace

The CoreSight debug and trace system offers the following features:
Altera Corporation
SPI, Texas Instruments
®
Microwire protocol
sample delay
rxd
on page 19-1
on page 19-1
on page 22-1
Synchronous Serial Protocol or National Semicon‐
®
Introduction to the Hard Processor System
cv_5v4
2016.10.28
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