Master Caching And Buffering Overrides - Altera cyclone V Technical Reference

cv_5v4
2016.10.28
Bit Name
hps2fpga
lwhp2fpga
Reserved
Related Information
remap on page 7-32
Description of the

Master Caching and Buffering Overrides

Some of the peripheral masters connected to the system interconnect do not have the ability to drive the
caching and buffering signals of their interfaces. The system manager provides registers so that you can
enable cacheable and bufferable transactions for these masters. The system manager drives the caching
and buffering signals of the following masters:
Master Peripheral
EMAC0 and EMAC1
USB OTG 0 and USB OTG
1
NAND flash
SD/MMC
At reset time, the system manager drives the cache and buffering signals for these masters low. In other
words, the masters listed do not support cacheable or bufferable accesses until you enable them after reset.
There is no synchronization between the system manager and the system interconnect, so avoid changing
these settings when any of the masters are active.
System Interconnect
Send Feedback
Bit Offset
3
Value Meaning
0 Accesses to the associated address range return an AXI decode
error to the master
1 The HPS-to-FPGA bridge slave port is visible to the L3 masters
4
Value Meaning
0 Accesses to the associated address range return an AXI decode
error to the master
1 The lightweight HPS-to-FPGA bridge slave port is visible to
the L3 masters
31:5 Must always be 0.
register
remap
System Manager Register
Group
emacgrp
usbgrp
nandgrp
sdmmcgrp
Master Caching and Buffering Overrides
Description
Register
l3master
l3master
l3master
l3master
7-13
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