Altera cyclone V Technical Reference page 136

cv_5v4
2016.10.28
mpumodrst Fields
Bit
4
l2
3
scuper
2
wds
1
cpu1
0
cpu0
permodrst
The PERMODRST register is used by software to trigger module resets (individual module reset signals).
Software explicitly asserts and de-asserts module reset signals by writing bits in the appropriate *MODRST
register. It is up to software to ensure module reset signals are asserted for the appropriate length of time
and are de-asserted in the correct order. It is also up to software to not assert a module reset signal that
would prevent software from de-asserting the module reset signal. For example, software should not assert
the module reset to the CPU executing the software. Software writes a bit to 1 to assert the module reset
signal and to 0 to de-assert the module reset signal. All fields are reset by a warm or cold reset. The reset
value of all fields is 1. This holds the corresponding module in reset until software is ready to release the
module from reset by writing 0 to its field.
Module Instance
rstmgr
Reset Manager
Send Feedback
Name
Resets L2 cache controller
Resets SCU and peripherals. Peripherals consist of the
interrupt controller, global timer, both per-CPU
private timers, and both per-CPU watchdogs (except
for the Watchdog Reset Status registers).
Resets both per-CPU Watchdog Reset Status registers
in MPU.
Resets Cortex-A9 CPU1 in MPU. It is reset to 1 on a
cold or warm reset. This holds CPU1 in reset until
software is ready to release CPU1 from reset by
writing 0 to this field. On single-core devices, writes
to this field are ignored.On dual-core devices, writes
to this field trigger the same sequence as writes to the
CPU0 field (except the sequence is performed on
CPU1).
Resets Cortex-A9 CPU0 in MPU. When software
changes this field from 0 to 1, it triggers the following
sequence: 1. CPU0 reset is asserted. cpu0 clkoff is de-
asserted 2. after 32 osc1_clk cycles, cpu0 clkoff is
asserted. When software changes this field from 1 to
0, it triggers the following sequence: 1.CPU0 reset is
de-asserted. 2. after 32 cycles, cpu0 clkoff is de-
asserted. Software needs to wait for at least 64 osc1_
clk cycles between each change of this field to keep
the proper reset/​clkoff sequence.
Base Address
0xFFD05000
Description
Register Address
0xFFD05014
3-25
permodrst
Access Reset
RW 0x0
RW 0x0
RW 0x0
RW 0x1
RW 0x0
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