Altera cyclone V Technical Reference page 800

11-62
staticcfg
Offset:
0x5058
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
lowpwrack Fields
Bit
1
selfrfshack
0
deeppwrdnack
staticcfg
This register controls configuration values which cannot be updated during active transfers. First configure
the
membl
write only.
Module Instance
sdr
Offset:
0x505C
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
Altera Corporation
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Name
This bit is a one to indicate that the controller is in a
self-refresh state.
This bit is set to a one after a deep power down has
been executed
and fields and then re-write these fields while setting the applycfg bit. The applycfg bit is
eccn
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Reserved
Description
Base Address
0xFFC20000
21 20 19 18
5 4 3 2
Access
Register Address
0xFFC2505C
SDRAM Controller Subsystem
cv_5v4
2016.10.28
17 16
1 0
selfr deeppwrd
fshac nack
k
RW 0x0
RW
0x0
Reset
RW 0x0
RW 0x0
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