Altera cyclone V Technical Reference page 952

Hard processor system
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14-6
BIU
Figure 14-2: Multiple–Block Read Operation
sdmmc_cclk_out
sdmmc_cmd
sdmmc_data
The following figure illustrates an example of a command token sent by the host in a multiple-block write
operation.
Figure 14-3: Multiple‑–Block Write Operation
sdmmc_cclk_out
sdmmc_cmd
sdmmc_data
BIU
The Bus Interface Unit (BIU) interfaces with the Card Interface Unit (CIU), and is connected to the level 3
(L3) interconnect and level 4 (L4) peripheral buses. The BIU consists of the following primary functional
blocks, which are defined in the following sections:
Altera Corporation
From Host
From Card
to Card
to Host
Command
Response
Data Block
Block Read Operation
Multiple Block Read Operation
From Host
From Card
to Card
to Host
Command
Response
Block Write Operation
Data from
Card to Host
CRC
Data Block
CRC
Data from
OK Response &
Host to Card
Busy from Card
Data Block
CRC
Busy
Multiple Block Read Operation
Stop Command
Stops Data Transfer
Command
Response
Data Block
CRC
Data Stop Operation
Stop Command
Stops Data Transfer
Command
Response
Data Block
CRC
Busy
Data Stop Operation
SD/MMC Controller
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cv_5v4
2016.10.28

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