Constraints And Limitations Of Use - Altera cyclone V Technical Reference

cv_5v4
2016.10.28
Related Information
Reset Manager
Taking the DMA Controller Out of Reset
When a cold or warm reset is issued in the HPS, the reset manager resets this module and holds it in reset
until software releases it.
After the Cortex-A9 MPCore CPU boots, it can deassert the reset signal by clearing the appropriate bits in
the reset manager's corresponding reset register. For details about reset registers, refer to "Module Reset
Signals".
Related Information
Reset Manager

Constraints and Limitations of Use

DMA Channel Arbitration
The DMAC uses a round-robin scheme to serve the active DMA channels. To ensure that the DMAC
continues to serve the DMA manager, it always serves the DMA manager prior to serving the next DMA
channel.
Note: You cannot alter the arbitration process of the DMAC.
DMA Channel Prioritization
The DMAC responds to all active DMA channels with equal priority. You cannot increase the priority of a
DMA channel over any other DMA channels.
Instruction Cache Latency
When a cache miss occurs, most of the delay is introduced by the memory containing the DMA code; the
DMAC adds minimal delay.
AXI Data Transfer Size
The DMAC can only perform data accesses up to 64 bits in width. If you program the
dst_burst_size
Related Information
Abort Sources
AXI Bursts Crossing 4 KB Boundaries
The AXI specification does not permit AXI bursts to cross 4 KB address boundaries. If you program the
DMAC with a combination of burst start address, size, and length that would cause a single burst to cross
a 4 KB address boundary, then the DMAC generates a pair of bursts with a combined length equal to that
specified. This operation is transparent to the DMAC channel thread program so that, for example, the
DMAC responds to a single
DMA Controller
Send Feedback
on page 3-1
on page 3-1
fields to be larger, the DMAC indicates a precise abort.
on page 16-23
instruction by generating the appropriate pair of AXI read bursts.
DMALD
Taking the DMA Controller Out of Reset
16-33
or
src_burst_size
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