Altera cyclone V Technical Reference page 12

TOC-12
2
I C Controller Programming Model.....................................................................................................20-16
2
I C Controller Address Map and Register Definitions....................................................................... 20-24
Document Revision History...................................................................................................................20-78
UART Controller............................................................................................... 21-1
UART Controller Features........................................................................................................................ 21-1
UART Controller Block Diagram and System Integration...................................................................21-2
UART Controller Signal Description...................................................................................................... 21-3
Functional Description of the UART Controller................................................................................... 21-4
DMA Controller Operation....................................................................................................................21-10
UART Controller Address Map and Register Definitions..................................................................21-14
Document Revision History...................................................................................................................21-56
General-Purpose I/O Interface......................................................................... 22-1
Features of the GPIO Interface.................................................................................................................22-1
GPIO Interface Block Diagram and System Integration...................................................................... 22-2
Functional Description of the GPIO Interface.......................................................................................22-3
GPIO Interface Programming Model..................................................................................................... 22-4
General-Purpose I/O Interface Address Map and Register Definitions.............................................22-4
Document Revision History...................................................................................................................22-22
Altera Corporation
DMA Controller Interface.......................................................................................................... 20-15
Clocks............................................................................................................................................ 20-15
Resets............................................................................................................................................. 20-15
Slave Mode Operation.................................................................................................................20-16
Master Mode Operation..............................................................................................................20-19
2
Disabling the I C Controller...................................................................................................... 20-20
DMA Controller Operation........................................................................................................20-20
I2C Module Address Map...........................................................................................................20-24
HPS I/O Pins...................................................................................................................................21-3
FPGA Routing................................................................................................................................ 21-3
FIFO Buffer Support...................................................................................................................... 21-4
UART(RS232) Serial Protocol...................................................................................................... 21-5
Automatic Flow Control............................................................................................................... 21-5
Clocks.............................................................................................................................................. 21-7
Resets............................................................................................................................................... 21-7
Interrupts.........................................................................................................................................21-7
Transmit FIFO Underflow.......................................................................................................... 21-11
Transmit Watermark Level......................................................................................................... 21-11
Transmit FIFO Overflow............................................................................................................ 21-12
Receive FIFO Overflow............................................................................................................... 21-13
Receive Watermark Level............................................................................................................21-13
Receive FIFO Underflow.............................................................................................................21-13
UART Module Address Map...................................................................................................... 21-14
Debounce Operation..................................................................................................................... 22-3
Pin Directions.................................................................................................................................22-3
Taking the GPIO Interface Out of Reset .................................................................................... 22-3
GPIO Module Address Map......................................................................................................... 22-4