Altera cyclone V Technical Reference page 917

13-96
page_cnt0
Bit
9
pipe_cpybck_cmd_comp
8
erase_comp
7
program_comp
6
load_comp
5
erase_fail
4
program_fail
3
time_out
2
dma_cmd_comp
1
RSVD
0
ecc_uncor_err
page_cnt0
Decrementing page count bank 0
Module Instance
nandregs
Offset:
0x430
Access:
RO
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
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Name
A pipeline command or a copyback bank command
has completed on this particular bank
Device erase operation complete
Device finished the last issued program command.
Device finished the last issued load command.
Erase failure occurred in the device on issuance of a
erase command. err_block_addr and err_page_addr
contain the block address and page address that failed
erase operation.
Program failure occurred in the device on issuance of
a program command. err_block_addr and err_page_
addr contain the block address and page address that
failed program operation.
Watchdog timer has triggered in the controller due to
one of the reasons like device not responding or
controller state machine did not get back to idle
A data DMA command has completed on this bank.
RSVD
If set, Controller will interrupt processor when Ecc
logic detects uncorrectable error.
0xFFB80000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
Description
Base Address
0xFFB80430
2016.10.28
Access Reset
RW 0x0
RW 0x0
RW 0x0
RW 0x0
RW 0x0
RW 0x0
RW 0x0
RW 0x0
R 0x0
RW 0x0
Register Address
NAND Flash Controller
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cv_5v4