Features Of The Sdram Controller Subsystem - Altera cyclone V Technical Reference

2016.10.28
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The hard processor system (HPS) SDRAM controller subsystem provides efficient access to external
SDRAM for the ARM Cortex-A9 microprocessor unit (MPU) subsystem, the level 3 (L3) interconnect,
and the FPGA fabric. The SDRAM controller provides an interface between the FPGA fabric and HPS.
The interface accepts Advanced Microcontroller Bus Architecture (AMBA) Advanced eXtensible Interface
(AXI) and Avalon
commands for the SDRAM, and manages the details of the SDRAM access.

Features of the SDRAM Controller Subsystem

The SDRAM controller subsystem offers programming flexibility, port and bus configurability, error
correction, and power management for external memories up to 4 GB.
• Support for double data rate 2 (DDR2), DDR3, and low-power DDR2 (LPDDR2) SDRAM
• Flexible row and column addressing with the ability to support up to 4 GB of memory in various
interface configurations
• Optional 8-bit integrated error correction code (ECC) for 16- and 32-bit data widths
• User-configurable memory width of 8, 16, 16+ECC, 32, 32+ECC
• User-configurable timing parameters
• Two chip selects (DDR2 and DDR3)
• Command reordering (look-ahead bank management)
• Data reordering (out of order transactions)
• User-controllable bank policy on a per port basis for either closed page or conditional open page
accesses
• User-configurable priority support with both absolute and weighted round-robin scheduling
• Flexible FPGA fabric interface with up to 6 ports that can be combined for a data width up to 256 bits
using Avalon-MM and AXI interfaces
• Power management supporting self refresh, partial array self refresh (PASR), power down, and
LPDDR2 deep power down
(24) The level of ECC support is package dependent.
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SDRAM Controller Subsystem
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Memory-Mapped (Avalon-MM) transactions, converts those commands to the correct
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