Debugging Hps Sdram In The Preloader - Altera cyclone V Technical Reference

cv_5v4
2016.10.28

Debugging HPS SDRAM in the Preloader

To assist in debugging your design, tools are available at the preloader stage.
• UART or semihosting printout
• Simple memory test
• Debug report
• Predefined data patterns
The following topics provide procedures for implementing each of the above tools.
Enabling UART or Semihosting Printout
UART printout is enabled by default. If UART is not available on your system, you can use semihosting
together with the debugger tool. To enable semihosting in the Preloader, follow these steps:
1. When you create the
2. Enable semihosting in the debugger, by typing
in the debugger.
SDRAM Controller Subsystem
Send Feedback
file in the BSP Editor, select SEMIHOSTING in the spl.debug window.
.bsp
Debugging HPS SDRAM in the Preloader
set semihosting enabled true
11-35
at the command line
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