Nand Flash Controller Features - Altera cyclone V Technical Reference

2016.10.28
cv_5v4
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The hard processor system (HPS) provides a NAND flash controller to interface with external NAND flash
memory in Altera
or as extra storage capacity for large applications or user data. The HPS NAND flash controller is based on
the Cadence Design IP

NAND Flash Controller Features

The NAND flash controller provides the following functionality and features:
• Supports one x8 NAND flash device
• Supports Open NAND Flash Interface (ONFI) 1.0
• Supports NAND flash memories from Hynix, Samsung, Toshiba, Micron, STMicroelectronics, and
Spansion
Note: The Spansion S34ML08G2 NAND flash memory is verified to work properly with the HPS.
• Supports error correction codes (ECCs) providing single-bit error correction and double-bit error
detection, with:
• Sector size programmable 512 byte (4-, 8-, or 16-bit correction) or 1024 byte (24-bit correction)
• Three NAND FIFOs - ECC Buffer, write FIFO and read FIFO
• Supports pipeline read-ahead and write commands for enhanced read and write throughput
• Supports devices with 32, 64, 128, 256, 384, or 512 pages per block
• Supports multiplane devices
• Supports page sizes of 512 bytes, 2 kilobytes (KB), 4 KB, or 8 KB
• Supports single layer cell (SLC) and multiple layer cell (MLC) devices with programmable correction
capabilities
• Provides internal direct memory access (DMA)
• Provides programmable access timing
Related Information
Supported Flash Devices for Cyclone V and Arria V SoC
For more information, refer to the supported NAND flash devices section on this page.
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system-on-a-chip (SoC) systems. You can use external flash memory to store software,
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NAND Flash Memory Controller.
®
NAND Flash Controller
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